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general description the max817/max818/max819 microprocessor (?) supervisory circuits simplify power-supply monitoring, battery control, and chip-enable gating in ? systems by reducing the number of components required. these devices are designed for use in +5v-powered systems. low supply current (11? typical) and small package size make these devices ideal for portable applications. the max817/max818/max819 are specif- ically designed to ignore fast transients on v cc . other supervisory functions include active-low reset, backup- battery switchover, watchdog input, battery freshness seal, and chip-enable gating. the selector guide below lists the specific functions available from each device. these devices offer two pretrimmed reset threshold volt- ages for ?% or ?0% power supplies: 4.65v for the l versions and 4.40v for the m versions. the max817/ max818/max819 are available in space-saving ?ax packages, as well as 8-pin dip/so. ________________________applications battery-powered computers and controllers embedded controllers intelligent instruments critical ? monitoring portable equipment ____________________________features precision supply-voltage monitor: 4.65v (max81_l) 4.40v (max81_m) 11a quiescent supply current 200ms reset time delay watchdog timer with 1.6sec timeout (max817/max818) battery-backup power switching; battery voltage can exceed v cc battery freshness seal on-board, 3ns gating of chip-enable signals (max818) uncommitted voltage monitor for power-fail or low-battery warning (max817/max819) manual reset input (max819) max817l/m, max818l/m, max819l/m* +5v microprocessor supervisory circuits ________________________________________________________________ maxim integrated products 1 wdi gnd pfo pfi 1 2 8 7 batt reset v cc out max817 dip/so/ max top view 3 4 6 5 _________________pin configurations 19-0486; rev 2; 2/00 part ? max817 _cpa max817_csa max817_cua 0? to +70? 0? to +70? 0? to +70? temp. range pin-package 8 plastic dip 8 so 8 ?ax ______________ordering information _____________________selector guide ordering information continued on last page. ? these parts offer a choice of reset threshold voltage. from the table below, select the suffix corresponding to the desired threshold and insert it into the blank to complete the part number. suffix reset threshold (v) l 4.65 m 4.40 feature max817 l/m active-low reset ? backup-battery switchover ? max818 l/m ? ? max819 l/m ? ? power-fail comparator ? watchdog input ? ? ? battery freshness seal ? ? manual reset input ? ? chip-enable gating ? pin-package 8-dip/so/ ?ax 8-dip/so/ ?ax 8-dip/so/ ?ax low-power, pin- compatible upgrades for: max690a/ max692a max703/ max704 typical operating circuit appears at end of data sheet. pin configurations continued at end of data sheet. *patents pending for free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800. for small orders, phone 1-800-835-8769.
max817l/m, max818l/m, max819l/m* +5v micr oprocessor supervisory circuits 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v cc = +4.75v to +5.5v for max81_l, v cc = +4.5v to +5.5v for max81_m, v batt = 2.8v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 1: the input voltage limits on pfi and wdi may be exceeded (up to 12v v in ) if the current into these pins is limited to less than 10ma. input voltage v cc , batt ..........................................................-0.3v to +6.0v all other pins (note 1).............................-0.3v to (v cc + 0.3v) input current v cc peak ..............................................................................1a v cc continuous .............................................................250ma batt peak .....................................................................250ma batt continuous .............................................................50ma gnd .................................................................................25ma output current out................................................................................250ma all other outputs .............................................................25ma out short-circuit duration.................................................10sec continuous power dissipation (t a = +70?) plastic dip (derate 9.09mw/? above +70?) .............727mw so (derate 5.88mw/? above +70?) ..........................471mw ?ax (derate 4.10mw/? above +70?) .....................330mw operating temperature ranges max81_ _c_a ......................................................0? to +70? max81_ _e_a ...................................................-40? to +85? storage temperature range .............................-65? to +160? lead temperature (soldering, 10sec) .............................+300? as applicable; ce in = 0v, wdi and mr unconnected v cc < v rst i out = 50ma i out = 5ma v cc = 0v, v out = 0v i out = 250?, v cc < (v batt - 0.2v) conditions mv 40 battery switchover hysteresis mv -20 battery switch threshold (v cc - v batt ) 20 v v batt - v batt - 0.1 0.02 v out in battery-backup mode ? 11 60 i supply supply current (excluding i out ) 11 45 v 0 5.5 operating voltage range, v cc , v batt (note 2) ? 100 batt to out on-resistance ? 510 v cc to out on-resistance v v cc - v cc - 0.5 0.25 v out output v cc - v cc - 0.05 0.025 ? 5.0 ? 1 batt leakage current, freshness seal enabled units min typ max symbol parameter v cc = 0v supply current in battery- backup mode (excluding i out ) 0.05 1.0 max81_ _c max81_ _e t a = +25? t a = t min to t max power-up power-down t a = +25? t a = t min to t max 5.5v > v cc > (v batt + 0.2v) batt standby current (note 3) -0.10 0.02 ? -1.00 0.02
electrical characteristics (continued) (v cc = +4.75v to +5.5v for max81_l, v cc = +4.5v to +5.5v for max81_m, v batt = 2.8v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) max817l/m, max818l/m, max819l/m* +5v microprocessor supervisory circuits _______________________________________________________________________________________ 3 v pfo = 0v v pfi > 1.30v, i source = 40?, v cc > 4.5v max81_m v pfi < 1.20v, i sink = 3.2ma, v cc > 4.50v max81_l wdi = gnd, time average from v rst , v cc falling at 10v/ms wdi = v cc , time average v cc = 5v max81_ _c, v cc = 1v, v cc falling, v batt = 0v, i sink = 50? v cc > v rst(max), i source = 800? v cc < v rst(min), i sink = 3.2ma v il = 0.4v, v ih = 0.8v cc conditions ? 250 500 pfo short-circuit current v cc - 1.5 v oh pfo output voltage v 0.4 v ol na -25 0.01 25 i pfi pfi input current mv 4 pfi input hysteresis v 1.20 1.25 1.30 v pft pfi input threshold ? -20 -15 wdi input current (note 5) 120 160 v 3.5 v ih wdi input threshold (note 4) 0.8 v il ns 50 t wdi wdi pulse width v 4.25 4.40 4.50 v rst reset threshold 4.50 4.65 4.75 sec 1.00 1.60 2.25 t wd watchdog timeout period ? 100 v cc to reset delay 0.3 mv 25 reset threshold hysteresis ms 140 200 280 t rp reset timeout period v cc - 1.5 v oh 0.4 v ol units min typ max symbol parameter max81_ _e, v cc = 1.2v, v cc falling, v batt = 0v, i sink = 100? v 0.3 reset output voltage 0.8 v 2.0 v il mr input threshold ? 1 mr pulse width v ih ns 100 mr pulse that would not cause a reset ns 120 mr to reset delay k ? 45 63 85 mr pull-up resistance reset and watchdog timer power-fail comparator (max817/max819 only) manual reset input (max819 only)
max817l/m, max818l/m, max819l/m* +5v micr opr ocessor supervisory circuits 4 _______________________________________________________________________________________ electrical characteristics (continued) (v cc = +4.75v to +5.5v for max81_l, v cc = +4.5v to +5.5v for max81_m, v batt = 2.8v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) power-down v cc = 5v i out = -1?, v cc = 0v, v batt = 2.8v i out = -100?, v cc = 0v enable mode disable mode conditions ? 15 reset to ce out delay 3.5 v il ce out input threshold v 0.8 v ih v 2.7 v oh ce out output v cc - 1v ? 40 150 ce in to ce out resistance (note 6) ? ?.005 ? ce in leakage current units min typ max symbol parameter note 2: either v cc or v batt can go to 0v if the other is greater than 2.0v. note 3: ??= battery-charging current, ??= battery-discharging current. note 4: wdi is internally serviced within the watchdog timeout period if wdi is left unconnected. note 5: wdi input is designed to be driven by a three-stated output device. to float wdi, the ?igh-impedance mode?of the output device must have a maximum leakage current of 10? and a maximum output capacitance of 200pf. the output device must also be able to source and sink at least 200? when active. note 6: the chip-enable resistance is tested with v cc = +4.75v for the max818l and v cc = +4.5v for the MAX818M. v ce in = v ce out = v cc /2. note 7: the chip-enable propagation delay is measured from the 50% point at ce in to the 50% point at ce out. disable mode, ce out = 0v ma 0.1 0.75 2.0 ce out short-circuit current (reset active) 50 ? source impedance driver, c load = 50pf ns 38 ce in to ce out propagation delay (note 7) chip-enable gating (max818 only)
max817l/m, max818l/m, max819l/m* +5v micr oprocessor supervisory circuits _______________________________________________________________________________________ 5 8 -40 40 supply current vs. temperature (no load) 12 max817/18/19-01 temperature (?) supply current ( a) -20 0 20 80 100 60 16 14 10 0 -40 40 battery supply current (backup mode) vs. temperature 20 80 100 120 140 160 max817/18/19-02 temperature ( c) battery supply current (na) -20 0 20 80 100 60 60 40 v cc = 0v v batt = 5.0v v batt = 2.8v v batt = 2.0v 0 -40 40 ce in to ce out on-resistance vs. temperature 20 80 max817/18/19-03 temperature ( c) ce in to ce out on-resistance ( ? ) -20 0 20 80 100 60 60 40 90 100 10 70 50 30 v ce in = 4v v ce in = 3v v ce in = 2v 0 -40 40 batt to out on-resistance vs. temperature max817/18/19-04 temperature ( c) batt to out on-resistance ( ? ) -20 0 20 80 100 60 50 100 150 200 250 300 v batt = 2.0v v batt = 2.8v v batt = 5.0v v cc = 0v 0 -40 40 v cc to reset propagation delay vs. temperature 200 max817/18/19-07 temperature ( c) v cc to reset propagation delay (ms) -20 0 20 80 100 60 300 400 500 100 v cc falling at: 0.25v/ms 1v/ms 10v/ms 3 -40 40 v cc to out on-resistance vs. temperature max817/18/19-05 temperature ( c) v cc to out on-resistance ( ? ) -20 0 20 80 100 60 4 5 6 7 180 -40 40 reset timeout period vs. temperature max817/18/19-06 temperature ( c) reset timeout period (ms) -20 0 20 80 100 60 190 200 210 220 1.50 -40 40 watchdog timeout period vs. temperature 1.60 max817/18/19-08 temperature ( c) watchdog timeout period (sec) -20 0 20 80 100 60 1.65 1.70 1.55 0 -40 40 battery freshness seal leakage current vs. temperature 10 max817/18/19-09 temperature ( c) leakage current (na) -20 0 20 80 100 60 15 20 5 __________________________________________typical operating characteristics (v cc = +5v, v batt = 3.0v, t a = +25?, unless otherwise noted.)
max817l/m, max818l/m, max819l/m* +5v microprocessor supervisory circuits 6 _______________________________________________________________________________________ 0 04 battery supply current vs. supply voltage max817/18/19-12 v cc (v) battery supply current ( a) 123 56 1 2 3 4 5 6 7 8 0 -40 40 ce in to ce out propagation delay vs. temperature max817/18/19-13 temperature ( c) ce in to ce out propagation delay (ns) -20 0 20 t pd - t pd + 80 100 60 1 2 3 4 5 6 7 20 max817/max819 pfi threshold vs. temperature max817/18/19-14 temperature ( c) threshold ( v ) -40 -20 0 60 80 100 40 1.244 1.242 1.240 1.246 1.248 1.250 1.252 1.254 4.3 -40 40 reset threshold vs. temperature 4.5 max817/18/19-10 temperature ( c) reset threshold (v) -20 0 20 80 60 4.6 4.7 4.4 max81_l max81_m 1000 1200 1400 1600 0 1 10 100 1000 10,000 maximum transient duration vs. reset threshold overdrive 200 max817/18/19-11 reset comparator overdrive, v th -v cc (mv) maximum transient duration ( s) 400 600 800 reset occurs above curve 20 max817/max819 pfi to pfo propagation delay vs. temperature max817/18/19-15 temperature ( c) propagation delay ( s ) -40 -20 0 60 80 100 40 28 29 30 31 32 33 ____________________________typical operating characteristics (continued) (v cc = +5v, v batt = 3.0v, t a = +25?, unless otherwise noted.)
max817l/m, max818l/m, max819l/m* +5v microprocessor supervisory circuits _______________________________________________________________________________________ 7 ______________________________________________________________pin description ground. 0v reference for all signals. 3 3 input supply voltage, +5v input. 2 2 supply output for cmos ram. when v cc rises above the reset threshold or above v batt , out is connected to v cc through an internal p-channel mosfet switch. when v cc falls below v batt , batt connects to out. 1 1 gnd 3 v cc 2 out 1 power-fail comparator output. when pfi is less than v pft or when v cc is below v batt , pfo goes low; otherwise pfo remains high. pfo is also used to enable the battery freshness seal (see battery freshness seal and power-fail comparator sections). 5 chip-enable input. the input to the chip-enable gating circuit. connect to ground if unused. 4 power-fail comparator input. when v pfi is below v pft or when v cc is below v batt , pfo goes low; otherwise, pfo remains high (see power-fail comparator section). connect to ground if unused. 4 pfo 5 ce in pfi 4 backup-battery input. when v cc falls below v batt , out switches from v cc to batt. when v cc rises above v batt , out reconnects to v cc . 8 8 active-low reset output. pulses low for 200ms when triggered and remains low whenever v cc is below the reset threshold or when mr is a logic low. it remains low for 200ms after v cc rises above the reset threshold, the watchdog triggers a reset, or mr goes low to high. 7 7 batt 8 reset 7 manual reset input. a logic low on mr asserts reset. reset remains asserted for as long as mr is held low and for 200ms after mr returns high. the active- low input has an internal 63k ? pull-up resistor. it can be driven from a ttl- or cmos-logic line or shorted to ground with a switch. leave open, or connect to v cc if unused. watchdog input. if wdi remains either high or low for longer than the watch- dog timeout period, the internal watchdog timer runs out and a reset is trig- gered. if wdi is left unconnected or is connected to a high-impedance three-state buffer, the watchdog feature is disabled. the internal watchdog timer clears whenever reset is asserted, wdi is three-stated, or wdi sees a ris- ing or falling edge. the wdi input is designed to be driven by a three-stated- output device with a maximum high-impedance leakage current of 10? and a maximum output capacitance of 200pf. the output device must also be capa- ble of sinking and sourcing 200? when active. 6 6 chip-enable output. ce out goes low only if ce in is low while reset is not asserted. if ce in is low when reset is asserted, ce out will remain low for 15? or until ce in goes high, whichever occurs first. ce out is pulled up to out in battery-backup mode. ce out is also used to enable the battery freshness seal (see battery freshness seal section). 5 mr 6 wdi ce out function name max817 max818 max819 pin
max817l/m, max818l/m, max819l/m* +5v micr opr ocessor super visor y cir cuits 8 _______________________________________________________________________________________ max817 max818 max819 v cc batt wdi pfi ce in 1.25v ce out gnd out reset this pin for max819 only. this section for max817/ max818 only. this section for max817/ max819 only. this section for max818 only. mr pfo chip-enable output control 1.25v reset generator battery freshness seal circuitry battery switchover circuitry watchdog timer figure 1. functional diagram
max817l/m, max818l/m, max819l/m* +5v microprocessor supervisory circuits _______________________________________________________________________________________ 9 _______________detailed description general timing characteristics designed for 5v systems, the max817/max818/ max819 provide a number of microprocessor (?) supervisory functions (see the selector guide on the first page). figure 2 shows the typical timing relation- ships of the various outputs during power-up and power-down with typical v cc rise and fall times. reset output a ?? reset input starts the ? in a known state. the max817/max818/max819 ? supervisory circuits assert a reset to prevent code-execution errors during power-up, power-down, and brownout conditions. reset is guaranteed to be a logic low for 0v < v cc < v rst if v batt is greater than 1v. without a backup bat- tery (v batt = gnd) reset is guaranteed valid for v cc 1v. once v cc exceeds the reset threshold an internal timer keeps reset low for the reset timeout period, t rp . after this interval reset returns high (figure 2). if a brownout condition occurs (v cc drops below the reset threshold), reset goes low. each time reset is asserted it stays low for at least the reset timeout peri- od. any time v cc goes below the reset threshold the internal timer clears. the reset timer starts when v cc returns above the reset threshold. reset both sources and sinks current. manual reset input (max819) many ?-based products require manual reset capabil- ity, allowing the operator, a test technician, or external logic circuitry to initiate a reset. on the max819, a logic low on mr asserts reset. reset remains asserted while mr is low, and for t rp (200ms) after it returns high. during the reset timeout period (t rp ), mr ? state is ignored if the battery freshness seal is enabled. mr has an internal 63k ? pull-up resistor, so it can be left open if not used. this input can be driven with ttl/cmos- logic levels or with open-drain/collector outputs. connect a normally open momentary switch from mr to gnd to create a manual reset function; external debounce circuitry is not required. if mr is driven from long cables or the device is used in a noisy environ- ment, connect a 0.1? capacitor from mr to gnd to provide additional noise immunity. note that mr must be high or open to enable the bat- tery freshness seal. once the battery freshness seal is enabled its operation is unaffected by mr . battery freshness seal the max817/max818/max819 battery freshness seal disconnects the backup battery from internal circuitry and out until it is needed. this allows an oem to ensure that the backup battery connected to batt will be fresh when the final product is put to use. to enable the freshness seal on the max817 and max819: 1) connect a battery to batt. 2) ground pfo. 3) bring v cc above the reset threshold and hold it there until reset is deasserted following the reset timeout period. 4) bring v cc down again (figure 3). use the same procedure for the max818, but ground ce out instead of pfo . once the battery freshness seal is enabled (disconnecting the backup battery from internal circuitry and anything connected to out), it remains enabled until v cc is brought above v rst . figure 2. power-up and power-down timing v cc ce out follows ce in *max817/max819 only. v out t rp v rst v batt v batt v batt v batt v rst v reset v ce out** v pfo* reset to ce out delay** pfo follows pfi ** max818 only. figure 3. battery freshness seal timing v cc reset t rp v rst v rst ce out (max818) (externally held at 0v) ce out state latched at 1/2 t rp and 3/4 t rp , freshness seal enabled pfo (max817/max819) (externally held at 0v) pfo state latched at 1/2 t rp and 3/4 t rp , freshness seal enabled
max817l/m, max818l/m, max819l/m* +5v microprocessor supervisory circuits 10 ______________________________________________________________________________________ on the max819, mr must be high or open to enable the battery freshness seal. once the battery freshness seal is enabled its operation is unaffected by mr . watchdog input (max817/max818) in the max817/max818, the watchdog circuit monitors the ?? activity. if the ? does not toggle the watchdog input (wdi) within t wd (1.6sec), reset asserts. the inter- nal 1.6sec timer is cleared by either a reset pulse or by toggling wdi, which can detect pulses as short as 50ns. the timer remains cleared and does not count for as long as reset is asserted. as soon as reset is released, the timer starts counting (figure 4). to disable the watchdog function, leave wdi uncon- nected or three-state the driver connected to wdi. the watchdog input is internally driven low during the first 7/8 of the watchdog timeout period, then momentarily pulses high, resetting the watchdog counter. when wdi is left open-circuited, this internal driver clears the 1.6sec timer every 1.4sec. when wdi is three-stated or left unconnected, the maximum allowable leakage cur- rent is 10? and the maximum allowable load capaci- tance is 200pf. chip-enable gating (max818) internal gating of the chip-enable (ce) signal prevents erroneous data from corrupting cmos ram in the event of an undervoltage condition. the max818 uses a series transmission gate from ce in to ce out (figure 5). during normal operation (reset not assert- ed), the ce transmission gate is enabled and passes all ce transitions. when reset is asserted, this path becomes disabled, preventing erroneous data from corrupting the cmos ram. the short ce propagation delay from ce in to ce out enables the max818 to be used with most ?s. if ce in is low when reset asserts, ce out remains low for typically 15? to permit the current write cycle to complete. chip-enable input (max818) the ce transmission gate is disabled and ce in is high impedance (disabled mode) while reset is asserted. during a power-down sequence when v cc passes the reset threshold, the ce transmission gate disables and ce in immediately becomes high impedance if the volt- age at ce in is high. if ce in is low when reset asserts, the ce transmission gate will disable 15? after reset asserts (figure 6). this permits the current write cycle to complete during power-down. figure 4. watchdog timing v cc t rp t wd reset wdi figure 6. chip-enable timing v batt v batt v cc t rp t rp 15 s v rst v rst v rst v rst v reset v ce in v ce out figure 5. chip-enable transmission gate ce in ce out p n out chip-enable output control reset generator battery switchover circuitry battery freshness seal circuitry max817 max818
max817l/m, max818l/m, max819l/m* +5v microprocessor supervisory circuits ______________________________________________________________________________________ 11 any time a reset is generated, the ce transmission gate remains disabled and ce in remains high impedance (regardless of ce in activity) for the reset timeout peri- od. when the ce transmission gate is enabled, the impedance of ce in appears as a 40 ? resistor in series with the load at ce out. the propagation delay through the ce transmission gate depends on v cc , the source impedance of the drive connected to ce in, and the loading on ce out (see typical operating characteristics ). the ce propagation delay is produc- tion tested from the 50% point on ce in to the 50% point on ce out using a 50 ? driver and a 50pf load capacitance (figure 7). for minimum propagation delay, minimize the capacitive load at ce out and use a low-output-impedance driver. chip-enable output (max818) when the ce transmission gate is enabled, the imped- ance of ce out is equivalent to a 40 ? resistor in series with the source driving ce in. in the disabled mode, the transmission gate is off and an active pull-up con- nects ce out to out (figure 5). this pull-up turns off when the transmission gate is enabled. power-fail comparator (max817/max819) the max817/max819 pfi input is compared to an inter- nal reference. if pfi is less than the power-fail threshold (v pft ), pfo goes low. the power-fail comparator is intended for use as an undervoltage detector to signal a failing power supply (figure 8). however, the comparator does not need to be dedicated to this function because it is completely separate from the rest of the circuitry. the power-fail comparator turns off and pfo goes low when v cc falls below v batt . during the reset timeout period (t rp ), pfo is forced high, regardless of the state of v pfi (see battery freshness seal section). if the com- parator is unused, connect pfi to ground and leave pfo unconnected. pfo can be connected to mr on the max819 so that a low voltage on pfi will generate a reset (figure 9). in this configuration, when the monitored voltage causes pfi to fall below v pft , pfo pulls mr low, causing a reset to be asserted. reset remains asserted as long as pfo holds mr low, and for t rp (200ms) after pfo pulls mr high when the monitored supply is above the programmed threshold. when pfo is connected to mr , it is not possible to enable the battery freshness seal. enabling the battery freshness seal requires mr to be high or open. once the battery freshness seal is enabled, it is no longer affected by pfo ? connection to mr . figure 7. ce propagation delay test circuit ce in batt ce out gnd max818 c l * * c l includes load capacitance, stray capacitance, and scope-probe capacitance. 50pf v cc +5v 50 ? 50 ? figure 8. using the power-fail comparator to generate a power-fail warning max817 max819 v warn = 1.25 power-fail-warning trip voltage r1 + r2 r2 pfi pfo r1 r2 p v cc v in nmi reset 1.25v reset +5v regulator ( )
max817l/m, max818l/m, max819l/m* +5v microprocessor supervisory circuits 12 ______________________________________________________________________________________ backup-battery switchover in a brownout or power failure, it may be necessary to preserve the contents of ram. with a backup battery installed at batt, the max817/max818/max819 auto- matically switch ram to backup power when v cc falls. these devices require two conditions before switching to battery-backup mode: 1) v cc must be below the reset threshold, and 2) v cc must be below v batt . table 1 lists the status of the inputs and outputs in bat- tery-backup mode. as long as v cc exceeds the reset threshold, out con- nects to v cc through a 5 ? pmos power switch. once v cc falls below the reset threshold, v cc or v batt (whichever is higher) switches to out. when v cc falls below v rst and v batt , batt switches to out through an 80 ? switch. when v cc exceeds the reset threshold, it is connected to the substrate, regardless of the voltage applied to batt (figure 10). during this time, the diode (d1) between batt and the substrate will conduct current from batt to v cc if v batt is 0.6v greater than v cc . when batt connects to out, backup mode is activated and the internal circuitry is powered from the battery (table 1). when v cc is just below v batt , the current draw from batt is typically 6?. when v cc drops to more than 1v below v batt , the internal switchover comparator shuts off and the supply current falls to less than 1?. __________applications information the max817/max818/max819 are protected for typical short-circuit conditions of 10sec or less. shorting out to ground for longer than 10sec destroys the device. decouple v cc , out, and batt to ground by placing 0.1? capacitors as close to the device as possible. connected to v out . current drawn from the battery is less than 1?, as long as v cc < v batt - 0.2v. v batt logic low disconnected from v out . v cc v r eset logic high. the open-circuit voltage is equal to v out . v ce out high impedance v ce in watchdog timer is disabled. v wdi connected to v batt through an internal 80 ? pmos switch. v out status signal table 1. input and output status in battery-backup mode figure 9. monitoring an additional supply by connecting pfo to mr. max819 v2 (reset) = 1.25 additional supply reset voltage r1 + r2 r2 r1 r2 p v cc v1 v2 reset pfi reset mr pfo ( ) figure 10. backup-battery-switchover block diagram sw1/sw2 sw3/sw4 condition v cc > reset threshold open closed closed open open closed v cc < reset threshold and v cc > v batt v cc < reset threshold and v cc < v batt reset threshold = 4.65v in max81_l reset threshold = 4.4v in max81_m out d3 substrate d1 d2 sw2 sw1 sw4 sw3 batt v cc max817 max818 max819
max817l/m, max818l/m, max819l/m* +5v microprocessor supervisory circuits ______________________________________________________________________________________ 13 watchdog input current the max817/max818 wdi inputs are internally driven through a buffer and series resistor from the watchdog counter (figure 1). when wdi is left unconnected, the watchdog timer is serviced within the watchdog timeout period by a low-high-low pulse from the counter chain. for minimum watchdog input current (minimum overall power consumption), leave wdi low for the majority of the watchdog timeout period, pulsing it low-high-low once within 7 / 8 of the watchdog timeout period to reset the watchdog timer. if instead wdi is externally driven high for the majority of the timeout period, up to 150? can flow into wdi. using a supercap as a backup power source supercaps are capacitors with extremely high capaci- tance values (on the order of 0.47f) for their size. since batt has the same operating voltage range as v cc , and the battery switchover threshold voltages are typically ?0mv centered at v batt , a supercap and simple charging circuit can be used as a backup power source. figure 11 shows a supercap used as a backup source. if v cc is above the reset threshold and v batt is 0.5v above v cc , current flows to out and v cc from batt until the voltage at batt is less than 0.5v above v cc . for example, if a supercap is connected to batt through a diode to v cc , and v cc quickly changes from 5.4v to 4.9v, the capacitor discharges through out and v cc until v batt reaches 5.1v typical. leakage cur- rent through the supercap charging diode and the internal power diode eventually discharges the supercap to v cc . also, if v cc and v batt start from 0.1v above the reset threshold and power is lost at v cc , the supercap on batt discharges through v cc until v batt reaches the reset threshold. battery-backup mode is then initiated and the current through v cc goes to zero. operation without a backup power source the max817/max818/max819 were designed for bat- tery-backed applications. if a backup battery is not used, connect v cc to out, and connect batt to ground. replacing the backup battery the backup power source can be removed while v cc remains valid, without danger of triggering a reset pulse, if batt is decoupled with a 0.1? capacitor to ground. as long as v cc stays above the reset thresh- old, battery-backup mode cannot be entered. adding hysteresis to the power-fail comparator (max817/max819) the power-fail comparator has a typical input hystere- sis of 4mv. this is sufficient for most applications where a power-supply line is being monitored through an external voltage divider (see monitoring an additional supply ). for additional noise margin, connect a resistor between pfo and pfi, as shown in figure 12. select the ratio of r1 and r2 such that pfi sees v pft when v in falls to the figure 11. using a supercap as a backup power source with a +5v ?0% supply supercap is a trademark of baknor industries. batt v cc out reset gnd to static ram to p 0.1f max817 max818 max819 +5v 100k figure 12. adding hysteresis to the power-fail comparator v cc gnd to p pfi pfo r1 r2 r3 *optional c1* v in +5v r1 + r2 r2 v h = 1.25v v trip = 1.25v + + || || r2 r3 r1 r2 r3 max817 max819 pfo 0v +5v v h v l 0v v trip v in ( ) r1 v l - 1.25 r3 5 - 1.25 = r2 1.25 ( )
max817l/m, max818l/m, max819l/m* +5v microprocessor supervisory circuits 14 ______________________________________________________________________________________ desired trip point (v trip ). resistor r3 adds hysteresis. it will typically be an order of magnitude greater than r1 or r2. the current through r1 and r2 should be at least 1? to ensure that the 25na (max) pfi input leakage current does not shift the trip point. r3 should be larger than 200k ? to prevent it from loading down the pfo pin. capacitor c1 adds additional noise rejection. monitoring an additional supply (max817/max819) the max817/max819 ? supervisors can monitor either positive or negative supplies using a resistor voltage divider to pfi. pfo can be used to generate an interrupt to the ? or to trigger a reset (figures 9 and 13). interfacing to ?s with bidirectional reset pins ?s with bidirectional reset pins, such as the motorola 68hc11 series, can contend with the max817/max818/ max819 reset output. if, for example, the reset out- put is driven high and the ? wants to pull it low, inde- terminate logic levels may result. to correct this, connect a 4.7k ? resistor between the reset output and the ? reset i/o, as in figure 14. buffer the reset output to other system components. negative-going v cc transients these supervisors are relatively immune to short-dura- tion, negative-going v cc transients (glitches) while issuing a reset to the ? during power-up, power-down, and brownout conditions. therefore, resetting the ? when v cc experiences only small glitches is usually not desirable. the typical operating characteristics show a graph of maximum transient duration vs. reset threshold overdrive for which reset pulses are not generated. the graph was produced using negative-going v cc pulses, starting at 3.3v and ending below the reset threshold by the magnitude indicated (reset threshold overdrive). the graph shows the maximum pulse width that a negative- going v cc transient can typically have without triggering a reset pulse. as the amplitude of the transient increases (i.e., goes farther below the reset threshold), the maxi- mum allowable pulse width decreases. typically, a v cc transient that goes 100mv below the reset threshold and lasts for 135? will not trigger a reset pulse. a 0.1? bypass capacitor mounted close to the v cc pin provides additional transient immunity. figure 13. monitoring a negative voltage max817 max819 v cc gnd pfi pfo r 1 r 2 v- note: v trip is negative 0v pfo 0v v trip v- +5v +5v r1 5 - 1.25 r2 1.25 - v trip = figure 14. interfacing to ?s with bidirectional reset i/o max817 max818 max819 buffered reset to other system components 4.7k v cc gnd v cc gnd reset reset
max817l/m, max818l/m, max819l/m* +5v microprocessor supervisory circuits ______________________________________________________________________________________ 15 ____pin configurations (continued) __________typical operating circuit wdi gnd ce out ce in 1 2 8 7 batt reset v cc out max818 dip/so/ max top view 3 4 6 5 mr gnd pfo pfi 1 2 8 7 batt reset v cc out max819 dip/so/ max 3 4 6 5 ce in* *ce in and ce out apply to max818 only. **wdi applies to max817/max818 only. batt reset i/o out cmos ram reset wdi** ce out* 0.1 f 0.1 f 0.1 f gnd max817 max818 max819 v cc address decode real- time clock a0?15 p +5v watchdog software considerations (max817/max818) to help the watchdog timer monitor software execution more closely, set and reset the watchdog input at different points in the program, rather than ?ulsing?the watchdog input high-low-high or low-high-low. this technique avoids a ?tuck?loop, in which the watchdog timer would contin- ue to be reset within the loop, keeping the watchdog from timing out. figure 15 shows an example of a flow diagram where the i/o driving the watchdog input is set high at the beginning of the program, set low at the beginning of every subroutine or loop, then set high again when the program returns to the beginning. if the program should ?ang?in any subroutine, the problem would quickly be corrected, since the i/o is continually set low and the watchdog timer is allowed to time out, triggering a reset or an interrupt. as described in the watchdog input current section, this scheme results in higher average wdi input current than does the method of leaving wdi low for the majority of the timeout period and periodically pulsing it low-high-low. figure 15. watchdog flow diagram start set wdi low subroutine or program loop, set wdi high return end
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 16 __________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 (408) 737-7600 2000 maxim integrated products printed usa is a registered trademark of maxim integrated products. max817l/m, max818l/m, max819l/m* +5v microprocessor supervisory circuits ordering information (continued) chip information ________________________________________________________package information transistor count: 719 ? these parts offer a choice of reset threshold voltage. from the table below, select the suffix corresponding to the desired threshold and insert it into the blank to complete the part number. part ? max817_epa max817_esa max818 _cpa 0? to +70? -40? to +85? -40? to +85? temp. range pin-package 8 plastic dip 8 so 8 plastic dip max818_csa max818_cua max818_epa -40? to +85? 0? to +70? 0? to +70? 8 so 8 ?ax 8 plastic dip max818_esa -40? to +85? 8 so max819 _cpa max819_csa max819_cua 0? to +70? 0? to +70? 0? to +70? 8 plastic dip 8 so 8 ?ax max819_epa max819_esa -40? to +85? -40? to +85? 8 plastic dip 8 so suffix reset threshold (v) l 4.65 m 4.40 l c a1 b dim a a1 b c d e e h l min 0.036 0.004 0.010 0.005 0.116 0.116 0.188 0.016 0 max 0.044 0.008 0.014 0.007 0.120 0.120 0.198 0.026 6 min 0.91 0.10 0.25 0.13 2.95 2.95 4.78 0.41 0 max 1.11 0.20 0.36 0.18 3.05 3.05 5.03 0.66 6 inches millimeters 8-pin max micromax small-outline package 0.65 0.0256 a e e h d 0.101mm 0.004 in 21-0036d

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